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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:58:31 03/09/2012 
-- Design Name: 
-- Module Name:    Timeout_UART - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Timeout_UART is
	port(	Klok			: in std_logic;
			Data_1 		: in std_logic;
			Data_full 	: in std_logic;
			Overflow		: out std_logic);
end Timeout_UART;

architecture RTL of Timeout_UART is
--	signal Timer integer range 0 to ? := 0;
begin
--	process(klok)
--		if rising_edge(klok)
--			if 

end RTL;

